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 Geplaatst: 28-06-2019 03:13:52 Onderwerp: The second approach in implementin k i |
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Definition of terms
Spiking Neural Network (SNN): it is a third generation technology used in development of modern processors with biological brain concept
Latency: Refers to total time taken for a processor to provide output to the user
Throughput: Refers to number of cycles that a processor can execute per second
Scalability of spiking neural network
Spiking Neural Networks (SNN) attempts to apply techniques of information processing like that of the mammalian brain by use of numerous parallel arrays of neurons. Neurons are meant to communicate via spike events. SNN implements embedded neuromorphic circuit networks with characteristics of high parallelism as well as low power consumption. SNN technology focuses on replacing and improving the traditional von Neumann computer paradigms which has serial based processing and high power consumption. Tradition von Neuman architecture has a problem characterized by weakness in lacking modularity and poor connectivity (Jim et al. Men's Air Max 97 CR7 University Red Sale , 2013). Traditional neuron interconnects poor processing capabilities due to the implementation of shared bus topologies that prohibits scalable hardware and software implementation of SNN. SNN provides a hierarchical network-on-chip (H-NoC) architecture that implements CNN hardware. CNN applications aim at addressing the scalability issue by implementing a modular array of numerous clusters of neurons by designing a hierarchical structure of low and high-level routers. The SNN has embedded chips, programmed using H-NoC technology. H-NoC chip incorporates spike traffic compression strategies that implement SNN traffic patterns. SNN provides scalability through operating between neurons which cause reduction of traffic overhead. It also improves throughput on the network. SNN provides high-level adaptive routing capabilities between clusters. It enables balancing of local and global traffic loads to enhance sustaining of throughput to prevent under bursting activity. Scalability provided by SNN through H-NoC chips under different scenarios can be explained through simulation and synthesis analysis using 65-nm CMOS technology. The output of the analysis proves high scalability through revealing characteristics such as high-throughput, low-cost per area Balenciaga x Air Max 97 Triple Black Sale , and low power consumption per cluster (Jim et al., 2013).
Comparison of optimizations on GPU and CPU architectures
Number of cipher text messages 512 1024 2048 4096
processor
Latency (ms) CPU core 0.17 0.3 2.3 14.9
(GPU) GTX580, MP 1.1 3.8 13.83 52.46
Through put (opss) CPU core 13 Air Max 97 CR7 Triple Black Sale ,924 3,301 438 67
(GPU) GTX580, MP 906 263 72 19
Peak (opss) CPU core 13 Women's Air Max 97 Premium Sneakers Light Bone Sale ,924 3,301 438 67
(GPU) GTX580, MP 322 Men's Air Max 97 Plus Racer Pink Hyper Magenta Sale ,167 74,732 12,044 1 Men's Air Max 97 Premium Shoes Blue Sale ,66
The figure represents a summary of RSA on CPU with a processing speed of 2.66 GHZ and GPU type GTX580. The testing operation involved using a single ciphertext message encrypted using RSA algorithm was released per launch. GPU performance indicated that it has a poor number of operations per second (throughput) as well as a poor time of execution (Latency). When the parallelism is improved using SNN GPU produces higher throughput that CPU (Sangjin, 2013).
Comparison of optimizations on GPU and CPU Architectures
Implementation of spiking neural networks on GPU
Spiking Neuron Networks (SNN) is implemented onto an array of Graphical Processing Unit (GPU) in three different approaches. The first approach is referred to as neuronal parallelism (N-Parallel) whereby each neuron element is mapped on Graphical Processing Unit and executed in parallel. Synaptic execution of each neuron is implemented sequentially on its Graphical Processing Unit. Implementing neuron using parallelism approach causes warp divergence making it ineffective for Graphical Processing Unit. For instance taking neuron 1 with the equivalent of 100 presynaptic links and get implemented it on thread one while neuron 2 with the equivalent of 200 presynaptic links is connected to thread 2 and get implemented on Graphical Processing Unit the following results shall be observed. The threads are in the warp and therefore they are implemented together and are computed together using a single instruction register. Thread 1 shall be pending waiting for thread 1 to finish leading to poor performance.
The second approach in implementing spiking neuron network into Graphical Processing Unit is called Synaptic Parallelism (S-parallelism) where each neuron is updated in parallel by different Graphical Processing Unit. Synaptic data and the information are distributed in all Graphical Processing Units. Neuron execution is implemented sequentially. Maximum parallelism is limited by some synaptic links that must be updated in a given time step. The third approach is called Neuronal Synaptic Parallelism (NS-parallel) whereby the approach combines both N-parallel and S-parallel (Hamid, et al. Air Max 97 OG Undefeated Shoes Black Sale , 2012). However, they are implemented at different stages in the simulation. The ns-parallel approach is preferred to other types of approaches since it is the best in the implementation of Graphical Processing Unit architecture. Each time neuron data and information require being updated N-parallel approach implemented. Every thread in GPU performs the process of updating each neuron data and information in parallel. When a spike is generated, the s-parallel approach is implemented to update synapses. S-parallel mapping is preferred within SMs because of availability of shared memory and fast synchronization.
Simulation of configurable multipurpose SNN
The simulation conducted used similar environments with an eight-core Intel Xeon CPU with a processor speed of 2.6 GHZ. Memory was 24 GB RAM and NVIDIA Tesla c2050 GPU Men's Air Max 97 Ultra Shoes All Black Sale , which had an internal memory of GPU RAM of 2687 Mbytes and a processor speed of 448 CUDA cores with a processor speed of 1.15 GHZ. In the simu
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